The present invention relates to sequential conversion-type A/D converters. In particular, this invention relates to sequential conversion-type ADCs with a control circuit for converting an analog input signal to a digital value, the control circuit proceeding sequentially from a leading bit through lower order bits of a sequential conversion register.
FIG. 10 and FIG. 11 are diagrams of the configuration and key parts, respectively, of a conventional sequential A/D converter.
FIG. 10 shows comparator 1 for comparing an analog input signal with the value of a D/A conversion result; sequential conversion register 2 for storing the result of A/D conversion and for decoding input data for a D/A converter; D/A converter 3 for converting the digital value (conversion result) of sequential conversion register 2 into an analog value; control circuit 4 for sequential conversion; and clock generator circuit 5 for A/D conversion. Analog input signal A, bit setting signals B supplied from control circuit 4 to sequential conversion register 2, one-bit conversion signal C, A/D conversion start signal D supplied from clock generator circuit 5 to both control circuit 4 and comparator 1, comparison voltage E output from D/A converter 3, and conversion complete signal F are also shown.
In FIG. 11 are shown latch circuit 6a for taking in data during a time interval "H" of an input clock signal (CLK) and latching data on the falling edge of the clock signal. Latch circuit 6a is set and reset by set signal S and reset signal R, respectively. Also shown is latch circuit 6b for taking in data during a time interval "L" of the input clock signal and latching data on the rising edge of the clock signal. Latch circuits 6a and 6b constitute a shifter S. Bits 70 to 77 and 7S of shifters S (which form the control circuit 4) are arranged in order from high to low. Bit setting signals B7 to B0 are supplied to bits a7 to a0, respectively, of sequential conversion register 2 and correspond to bit setting signals B of FIG. 10. In other words, control circuit 4 is constructed of shifters S, each consisting of latch circuits 6a and 6b connected to each other in a cascade manner and forming each of bits 77 to 70 and 7S.
Next, the operation of the A/D converter will be described. A/D conversion start signal D becomes active at the start of A/D conversion, and shifter S of bit 77 of control circuit 4 is set. Thereby, bit setting signal B7 becomes active in synchrony with a change in a one-bit conversion signal so that the leading bit a7 is set to "1" and bits a6 to a0 of sequential conversion register 2 are set to "0." At this time, a digital value of sequential conversion register 2 is decoded into an analog value (comparison voltage E) by D/A converter 3. Comparison voltage E and analog input voltage A, input from outside, are compared by comparator 1 in response to one-bit conversion signal C. Only when comparison voltage E from D/A converter 3 is higher than analog input signal A does the comparison result clear the value of bit a7 which has been set to "1" and resets it to "0". In this way, the conversion of bit a7 is first performed. Thereafter, for the conversion of bit a6, one-bit conversion signal C becomes active again, whereby the "1" of bit 77 is shifted to bit 76, and "0" is latched into bit 77. This activates only bit setting signal B6, and bit a6 is set to "1." Comparison between analog input voltage A and comparison voltage E from D/A converter 3 (decoded with a7 set to "1" or "0", a6 to "1", and a5 to a0 to "0") is performed by comparator 1 in response to one-bit conversion signal C. Like the conversion of bit a7, only when comparison voltage E is higher than analog input voltage A is bit a6 cleared.
In this manner, the "1" of bit 77 at the start of conversion is shifted from bit 76 to bit 70 of shifters S in response to one-bit conversion signal C. Thereby bit a7 to bit a0 are sequentially set to "1."
Comparison between comparison voltage E output and decoded by D/A converter 3 and analog input voltage A is repeated for bits a7 to a0, and bits a7 to a0 are kept at "1" or cleared to "0". In this way, the value of each bit is determined, and a single A/D conversion result is obtained in sequential conversion register 2. Furthermore, when the data is shifted up to bit 7S, conversion complete signal F becomes active to complete conversion.
Such a sequential conversion-type A/D converter is used to convert input data such as the water temperature of an engine radiator (TR), an engine boost pressure (BP), or car acceleration (MP) into digital signals. Such input data is selectively input into comparator 1 by clock generator circuit 5 as analog signal A for conversion into a digital signal.
Since the conventional sequential conversion-type A/D converter is structured as described above, a predetermined conversion time is always required for the conversion of an analog input signal which shows small changes. Say, for example, that the water temperature of the radiator (TR) changes slightly a predetermined time period tl after the start of an engine, as shown in FIG. 13. Despite the small change over a predetermined range P from TR1 to TR2, all the bits of sequential conversion register 2, from the leading bit sequentially downward, are set to "1," during sequential conversion. Therefore, it takes time to obtain the result of conversion.